SHANGHAI -- Semiconductor Manufacturing International Corporation ("SMIC") announced that a full set of Electrostatic Discharge (ESD) protection service, including documents, checklists, PERC Suite, floor plan review, and risk management services, has been offered to IC design customers to enhance the whole chip ESD design and ensure their first silicon success.
Along with the rapid progress of semiconductor manufacturing process technologies, ESD has become a more serious and challenging problem when the dimension of device shrinks to sub-65nm. Just depending on I/O design is not sufficient for ESD protection design, especially in the interface of different power domain circuits. The designers become more concerned about the ESD problem since the gate oxide becomes more easily damaged as the dimension are reduced. Therefore, the conception of whole chip ESD design should be recognized.
In order to help customers to manage ESD risk and implement the whole chip ESD design, SMIC provides 3 lines of defense designated on ESD protection: first, SMIC offers a whole set of documents and checklists which customers must follow during design stage to plan their chip level ESD protection in different process technologies at SMIC. Second, a newly developed Mentor PERC Suite is provided for ESD protection automatic check at chip level when taped out. Last but not least, SMIC provides ESD floor plan review and risk management services upon customers' requests. The floor plan review covers the IO application, placement/route and final GDS review for the customer who uses SMIC's IO library. All the solutions are aimed to improve chip's ESD protection performance.
"Nowadays, good ESD protection is the result of collaborative effort from robust I/O design service by the foundry, full chip level ESD protection scheme by customers and conscientious IP level ESD protection by third party providers," said Dr. Tianshen Tang, senior vice president of SMIC's Design Service Center. "At SMIC, we thoroughly investigate to ensure customers' ease of access to all SMIC ESD protection solutions. Several years ago, SMIC had taken the lead in carrying out the comprehensive ESD research in the industry, and not only solved the technical problems with experts and suppliers, but also explored and practiced the ESD protection design and test processes as well as business model with important clients. We accumulated a lot of successful experiences. In 2013, the pass rate of ESD floor plan review cases by SMIC exceeded 95%. Based on the successful trial operation, SMIC officially announces the launch of overall ESD protection design services. It symbolizes our service abilities for IC design customers have become more professional, standardized, advanced and comprehensive."
For more information, visit http://www.smics.com