Leti, a research institute of CEA-Tech, and software/IP provider Silvaco are partnering on a three-year project to create innovative and unified SPICE compact models for the design of advanced circuits using nanowire and nanosheet technologies. The new predictive and physical compact model under development, Leti-NSP, builds on 15 years of model development, including the popular Leti-UTSOI model for FD-SOI technology. The Leti-NSP compact model uses a novel methodology for the calculation of the surface potential, including quantum confinement. The model can handle arbitrary cross-section shapes of stacked planar and vertical GAA MOSFETs (circular, square, rectangular). It provides an excellent tool for design exploration of nanowire and nanosheet device architectures.
The three-year collaboration will make the new device models available to designers through SmartSpice, Silvaco’s high-performance parallel SPICE simulator for use by circuit designers. The corresponding model-parameters extraction flow will be implemented in Utmost IV, Silvaco’s database-driven environment for characterizing semiconductor devices, to ensure an accurate fit between simulated and measured device characteristics.
Accuracy of analysis at the nanometer scale is required for co-optimization of silicon process technology and circuit performance. In addition to accurate device characterization and simulation, a complete solution includes TCAD simulation, and 3D parasitic extraction. For more details, visit CEA-Leti and Silvaco.