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3DIC Technology Using Through Silicon Vias Improves Form Factor In Sensor Apps

June 10, 2016 By: Helmut Hofstaetter, ams AG, Andreas Wild, ams AG

Sensors Insights by Helmut Hofstaetter & Andreas Wild

Smaller form factor, excellent functionality, improved performance and lower bill of material (BOM) are the key challenges for system engineers developing complex electronic products such as sensor and sensor interface applications. While die size reduction can be realized by using smaller process nodes with higher integration densities, a system miniaturization can be achieved by using advanced packaging technologies. The increasing demand for higher system integration has pushed the traditional assembly service providers but also the semiconductor companies to develop more innovative and more advanced packaging technologies.

One of the most promising and but also challenging technologies is the 3-dimensional integration of integrated circuits (3DIC) using through Silicon Vias (TSV). 3DIC technology is now widely used in digital ICs (e.g. stacking of memory ICs, image sensors, and others), its design and manufacturing approach has been successfully proven in the digital world. So how can 3DIC technology be successfully implemented in analog and mixed-signal dominated sensor ICs?

Currently pioneering analog and mixed-signal IC developers are starting to recognize substantial benefits in implementing analog 3DIC designs. Smart sensor and sensor interface products target various applications in Industry 4.0, Smart Cities or the Internet of Things (IoT). TSV and backside redistribution layer (BRDL) are very useful technologies for the replacement of traditional gold wire bonding in various chip-stacking technologies. 3D integration technologies, in particular specialty analog TSV technologies from leading foundry service providers, in combination with front-side or back-side RDL, offer more functionality in a reduced board footprint, improve performance due to shorter interconnects and achieve a higher level of integration. In particular the small size of the TSV package technology (total height in the range of 0.32 mm) addresses the small form factor requirement in wearable products such as smart watches or smart glasses.

TSV technologies also offer a higher level of flexibility in combining different wafers or technologies: Wafer to wafer stacking of a digital wafer, e.g. manufactured in a 45-nm process, and an analog wafer (e.g. 180 nm), stacking of MEMS devices or photo sensors and photo diode arrays, just to name a few.

Analog 3DIC technologies typically address sensor applications by creating an electrical connection from the front side of a chip to the back side of the IC. In numerous sensor applications such as optical, chemical, gas or pressure sensors, the sensing area is on the CMOS side (top side of the wafer). The most commonly used connection between die and lead frame is wire bonding (figure 1). Independent whether a plastic package is used or the die is directly bonded on the PCB or flex, for certain applications with exposed sensing area, wire bonding is not the ideal solution. Using specialty foundry service providers' proprietary TSV technology, the bond wires can be replaced by using TSVs, a backside RDL and Chip Scale Packaging (WLCSP) (figure 2).

Fig. 1: Sensor chip with standard wire bonding
Fig. 1: Sensor chip with standard wire bonding

Fig. 2: Sensor chip with backside connection using TSV
Fig. 2: Sensor chip with backside connection using TSV

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