HDL Code Generation for MATLAB from MathWorks

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March 11, 2012

MathWorks, Natick, MA, has introduced HDL Coder, which automatically generates HDL code from MATLAB, and HDL Verifier, which includes FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs and provides HDL code generation and verification across MATLAB and Simulink. HDL Coder provides portable synthesizable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. it also provides traceability between Simulink models and generated HDL code. HDL Verifier supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards; provides co-simulation interfaces linking MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and QuestaHDL simulators; and lets you verify that the HDL implementation matches the MATLAB algorithms and Simulink system specifications.


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