Electronics & Computers

Clock Buffers Take A Slice Out Of Additive Jitter

Clock Buffers Take A Slice Out Of Additive Jitter
Texas Instruments Inc.
March 13, 2014

The four-output LMK00334 and eight-output LMK00338 HCSL clock fanout buffers boast 70% lower additive jitter than comparable devices. Both devices support PCIe Gen1/2/3 interface standards and promise to simplify clock tree design for high speed wireless communications and data center systems. Features include an additive jitter of 30 fs at100 MHz (PCIe 3.0) and 86 fs at 12 kHz to 20 MHz (HCSL at156.25 MHz), a PSRR of -75 dBc at100 MHz, and two universal inputs operating up to 400 MHz that accept CML, LVPECL, LVDS, SSTL, HSTL, HCSL or single-ended clocks and crystal oscillators. Datasheets for the LMK00334 and LMK00338 are available, respectively, at http://www.ti.com/lit/ds/symlink/lmk00334.pdf and http://www.ti.com/lit/ds/symlink/lmk00338.pdf

Texas Instruments Inc.
Dallas, TX


CompanyTexas Instruments Inc.
CountryUnited States (USA)




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