Xilinx and Open-Silicon Announce Hybrid Memory Cube Controller IP for All Programmable FPGAsApril 21, 2014
New Open-Silicon HMC Controller IP for Xilinx Virtex-7 FPGAs enables system developers to utilize high memory bandwidth and decrease time to market
SAN JOSE, CA -- Xilinx, Inc. and Open-Silicon, Inc., both founding developer members of the Hybrid Memory Cube Consortium (HMCC), announced Hybrid Memory Cube (HMC) controller IP for Xilinx Virtex-7 FPGAs. The high-performance nature of Virtex-7 FPGAs enables system developers to take advantage of the ultra-high memory bandwidth of the Hybrid Memory Cube and utilize the host-side IP to decrease time to market while providing over 1 Tb/s of serial bandwidth.
Hybrid Memory Cube is a high performance memory solution that delivers unprecedented levels of bandwidth, power efficiency and reliability for networking and computing systems. The Hybrid Memory Cube Consortium successfully defined an industry standard HMC interface in April 2013 and continues to work to build the ecosystem to enable its widespread adoption. Today's joint announcement of host-side controller IP availability for Xilinx FPGAs marks another key date in the evolution of this leading edge technology.
"The availability of new host-side HMC Controller IP furthers the widespread adoption of this revolutionary technology," said Tom Eby, vice president, Compute and Networking Business Unit at Micron. "We are pleased that Xilinx and Open-Silicon have provided a new solution for this growing market."
The Open-Silicon HMC Controller IP offers a seamless interface to HMC. The high-performance controller offers an ultra-low latency core coupled with a flexible user interface. Optimized for Xilinx Virtex-7 FPGA implementation, the IP supports HMC links operating at 12.5 Gb/s per lane. The HMC controller has been tested on Xilinx Virtex-7 FPGAs and, along with the accompanying software stack, allows for the quick integration and evaluation of the HMC technology and performance testing of the HMC links.
"The industry's highest performance HMC interface at 12.5 Gb/s is now enabled by a combination of Xilinx's Virtex-7 FPGAs and Open-Silicon's HMC IP, allowing our mutual customers to achieve extremely high throughput for next generation designs," said Dave Myron, senior director of FPGA product management and marketing at Xilinx.
"We joined HMCC as one of the first developers with the intent to help bring this exciting technology to market with a level of quality that Open-Silicon is known for," said Taher Madraswala, COO, Open-Silicon. "Our networking, computing, and industrial customers are actively seeking ultra-high bandwidth memory solutions. The HMC Controller IP will allow customers to jumpstart their next-generation product development featuring this new high-performance memory solution."
The Open-Silicon HMC Controller IP is available now, for more information, visit http://www.open-silicon.com/open-silicon-ips/hmc
For more information, visit Open-Silicon's website at http://www.open-silicon.com or call 408-240-5700.
For more Xilinx information, visit http://www.xilinx.com
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