Tech & Product

Microsemi & OneSpin Target High-reliability Design Verification with Formal-based FPGA Equivalency Checking Solution

March 23, 2015

ALISO VIEJO and SAN JOSE, CA -- Microsemi Corporation and OneSpin Solutions announce that OneSpin 360 Equivalence Checking (EC)-FPGA verification solution now fully supports Microsemi's Libero System-on-Chip (SoC) design flow.

Equivalency checking has become a critical component in the verification of high-reliability designs such as safety critical components, ensuring that no issues are introduced during the design refinement process. OneSpin's EC-FPGA product augments Microsemi's Libero design flow to ensure the functional consistency of high-reliability designs throughout design refinement, significantly reducing the risk of an end-product fault.

"OneSpin Solutions has created innovative formal-based design verification and equivalence checking solutions that are being used to fully vet some of the most safety critical designs in production today," said Bruce Weyer, vice president and business unit manager at Microsemi. "We believe that by including equivalence checking as part of the design flow, we will better meet our customers' stringent requirements for high-reliability designs."

Microsemi has seen tremendous adoption of its Libero SoC design software for its SmartFusion2 and IGLOO2 FPGAs in 2013, and now has over 44,000 licenses granted year to date. This is being driven by the inherent value the market is seeing with Microsemi FPGAs, which are positioned competitively in mainstream applications for communication, industrial, aerospace and defense markets.

Erik Matusek, the Safety System Platform Manager at Westinghouse Electric Company, LLC said, "The Microsemi ProASIC3 FPGA is a core component of the Advanced Logic System, and use of the OneSpin 360 Equivalence Checker is an integral part of our FPGA development process for nuclear safety systems."

By leveraging OneSpin's equivalence checker with Microsemi's industry-leading design flow, designers can be certain that when they implement the most aggressive design flow optimizations to improve FPGA device power consumption, performance and area utilization, they do not introduce functional errors. The tool verifies functional equivalence between the register transfer level (RTL) code and the netlist prior to FPGA download, thus reducing prototype verification requirements and ensuring that no design flow bugs appear in the final device.

"High reliability is a critical consideration for designers employing Microsemi devices and the reason why equivalence checking is an important technology in this flow," said Dr. Raik Brinkmann, OneSpin Solutions' president and chief executive officer. "Given our own expertise in this area, we are delighted to cooperate with Microsemi on a flow that targets the sharp-end of verification needs, high reliability."

About the OneSpin 360 EC-FPGA Verification Solution

OneSpin 360 EC-FPGA eliminates design flow-generated errors in FPGAs, uniquely supporting complex sequential optimizations with an easy-to-use solution that accelerates schedules, reduces risk and increases product quality. The tool includes support for Verilog, SystemVerilog, VHDL, EDIF and mixed languages, and runs on the Linux and Solaris platforms. It also supports Microsemi's SmartFusion2 SoC FPGAs, IGLOO2 and IGLOO FPGAs, ProASIC3 and Fusion FPGA devices.

About Microsemi SmartFusion2 SoC FPGAs

Microsemi's SmartFusion2 SoC FPGAs are the only devices that address fundamental requirements for advanced security, high reliability and low power in critical industrial, military, aviation, communications and medical applications. SmartFusion2 integrates an inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM® Cortex™-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and industry-required high-performance communication interfaces all on a single chip.

About Microsemi IGLOO2 FPGAs

Microsemi's IGLOO2 FPGAs continue the company's focus on addressing the needs of today's cost-optimized FPGA market by providing a LUT-based fabric, 5G transceiver, high speed GPIO, block RAM, high-performance memory subsystem, and DSP blocks in a differentiated, cost and power optimized architecture. This next generation IGLOO2 architecture offers up to five times more logic density and three times more fabric performance than its predecessors and combines a non-volatile Flash-based fabric with the highest number of general purpose I/O, 5G SERDES interfaces and PCIe end points when compared to other products in its class. IGLOO2 FPGAs offer best-in-class feature integration coupled with the lowest power, highest reliability and most advanced security in the industry.

Pricing and Availability
The combined design flow is available immediately. Pricing is available upon request.

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