Cadence to Enhance High-Level Synthesis Offering with Acquisition of Forte Design SystemsFebruary 6, 2014
SAN JOSE, CA -- Cadence Design Systems, Inc. announced that it has entered into a definitive agreement to acquire Forte Design Systems, a provider of SystemC-based high-level synthesis (HLS) and arithmetic IP.
• High-Level Synthesis has moved beyond early adopters toward mainstream adoption by market-leading system and semiconductor companies
• Forte Design Systems provides a production-proven, compelling high-level synthesis solution and high quality arithmetic IP
• Cadence C-To-Silicon Compiler provides high quality of results for mixed control and datapath designs, with built-in RTL synthesis and incremental ECO support
Driven by increasing IP complexity and the need for rapid retargeting of IP to derivative architectures, the high-level synthesis market segment has grown beyond early adopters toward mainstream adoption, as design teams migrate from hand-coded RTL design to SystemC-based design and verification. The addition of Forte's synthesis and IP products to the Cadence C-to-Silicon Compiler offering will enable Cadence to further drive a SystemC standard flow for design and multi-language verification.
"Growth in the high-level synthesis market segment is accelerating," said Charlie Huang, senior vice president of the System & Verification Group and Worldwide Field Operations at Cadence. "HLS tools are now addressing a broader application space and producing equal or better quality of results than hand-coded RTL, fueling worldwide adoption and production deployment amongst leading companies. We look forward to welcoming Forte's technology and skilled team to Cadence to help address this opportunity."
Forte brings high quality of results (QoR) for datapath-centric designs, world-class arithmetic IP, valuable SystemC IP and IP development tools. Forte's Cynthesizer HLS product features strong support for memory scheduling, especially for highly parallel or pipelined designs. These strengths complement the high QoR for transaction-level modeling, under-the-hood RTL synthesis and incremental ECO support featured by Cadence C-to-Silicon Compiler.
"Cadence and Forte have compatible approaches to high-level synthesis, and a similar vision to enable migration of design to the system level," said Sean Dart, CEO of Forte. "The combination will benefit customers through a standardized system-level flow, improved product capabilities for both customer bases, and integration all the way to silicon."
The acquisition is expected to close within 30 days. Taking into account the effects of merger accounting, the transaction is expected to be slightly accretive to Cadence's 2014 results of operations and accretive in 2015 and beyond. Terms of the transaction were not disclosed.
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